1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing interconnections thereof, and more particularly to a semiconductor device having a damascene structure and a method of manufacturing interconnections thereof.
2. Description of the Related Art
The damascene technology used in processes of fabricating semiconductor devices is capable of easily planarizing interlayer insulation films and forming interconnections, and is applicable to the formation of interconnections made of conductive materials such as copper (Cu), etc. which are difficult to etch according to reactive ion etching (RIE).
Damascene structures include a single damascene structure and a dual damascene structure. The single damascene structure is produced by embedding a conductive layer in a via hole and an interconnection groove by film deposition, and then polishing off an excessive deposit of the conductive layer to produce a via hole filling and an interconnection separately. The dual damascene structure is produced by forming a groove in a region where a via hole and an interconnection will be produced, embedding a conductive layer in the groove by film deposition, and then polishing off an excessive deposit of the conductive layer to produce a via hole filling and an interconnection simultaneously.
A process of fabricating a semiconductor device according to the single damascene technology will be described below with reference to FIGS. 1a through 1j of the accompanying drawings.
First, as shown in FIG. 1a, oxide film 102 is deposited on silicon substrate 101 with circuit components formed therein. INTERCONNECTIONS THEREOF
Then, as shown in FIG. 1b, groove 103 is formed by etching in a portion of oxide film 102 where a contact will be produced.
As shown in FIG. 1c, barrier layer 104 is deposited on the entire surface of oxide film 102 including groove 103.
As shown in FIG. 1d, conductive layer 105 of tungsten is deposited on barrier layer 104, thereby embedding tungsten in groove 103.
Thereafter, the entire assembly is polished by CMP (Chemical Mechanical Polishing) to remove conductive layer 105 and barrier layer 104 except groove 103, thus 25 producing contact 106 in groove 103, as shown in FIG. 1e. 
Then, as shown in FIG. 1f, oxide film 107 is deposited on oxide film 102 with contact 106 provided therein.
As shown in FIG. 1g, groove 108 is formed by etching in oxide film 107 over contact 106.
As shown in FIG. 1h, barrier layer 109 is deposited on the entire; surface of oxide film 107 including groove 108.
Then, as shown in FIG. 1i, conductive layer 110 of copper is deposited on barrier layer 109, thereby embedding copper in groove 108.
Thereafter, the entire assembly is polished by CMP to remove conductive layer 110 and barrier layer 109 except groove 108, thus producing interconnection 111 in groove 108, as shown in FIG. 1j. 
The above successive steps of the process produce a semiconductor device having a single damascene structure. If a semiconductor device comprising a plurality of layers is to be fabricated according to the single damascene technology, then the above process is repeated to produce a semiconductor device of single damascene structure which comprises a plurality of layers.
A process of fabricating a semiconductor device according to the dual damascene technology will be described below with reference to FIGS. 2a through 2f of the accompanying drawings.
First, as shown in FIG. 2a, contact 106 and interconnection 111 are formed according to the single damascene technology as shown in FIGS. 1a through 1j. 
Then, as shown in FIG. 2b, oxide film 112 is deposited on oxide film 107 with interconnection 111 formed therein.
Then, as shown in FIG. 2c, groove 113 is formed by etching in a portion of oxide film 112 where a via and an interconnection will be produced.
As shown in FIG. 2d, barrier layer 114 is deposited on the entire surface of oxide film 112 including groove 113.
As shown in FIG. 2e, conductive layer 115 of copper is deposited on barrier layer 114, thereby embedding copper in groove 113.
Thereafter, the entire assembly is polished by CMP to remove conductive layer 115 and barrier layer 114 except groove 113, thus producing via 116 and interconnection 117, as shown in FIG. 2f. 
The above successive steps of the process produce a semiconductor device having a dual damascene structure. If a semiconductor device comprising a plurality of layers is to be fabricated according to the dual damascene technology, then the above process as shown in FIGS. 2b through 2f is repeated to produce a semiconductor device of dual damascene structure which comprises a plurality of layers.
A semiconductor device which comprises a plurality of layers includes a portion where interconnections and vias are formed linearly across several layers for heat radiation.
A semiconductor device which comprises a plurality of layers that has been fabricated according to the single damascene technology only will be described below with reference to FIG. 3 of the accompanying drawings.
As shown in FIG. 3, the semiconductor device comprises silicon substrate 101, contact 121a of tungsten and vias 121b-121e of tungsten, and interconnections 122a-122e of copper. Contact 121a, vias 121b-121e, and interconnections 122a-122e are deposited linearly on silicon substrate 101.
Tungsten has a relatively low heat conduction capability.
Therefore, the interconnection structure shown in FIG. 3 is liable to suffer thermal breakdown, thermal runaway, and latch-up, and has low ESD (Electrostatic Discharge) resistance.
A semiconductor device which comprises a plurality of layers that has been fabricated according to the dual damascene technology only will be described below with reference to FIG. 4 of the accompanying drawings.
As shown in FIG. 4, the semiconductor device comprises silicon substrate 101, contact 121a of tungsten and vias 131a-131d of copper, and interconnections 122a-122e of copper. Contact 121a, vias 131a-131d, and interconnections 122a-122e are deposited linearly on silicon substrate 101.
Copper is of weak tensile strength and weak mechanical strength.
Therefore, when the semiconductor device with linearly arranged vias 131a-131d undergoes a bonding process, the region where vias 131a-131d are formed is apt to be broken under the bonding pressure.
It is therefore an object of the present invention to provide a semiconductor device which has large mechanical strength and excellent heat radiation capability, and a method of fabricating such a semiconductor device.
According to the present invention, a semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and ground lines and vias therebeneath formed of copper according to a dual damascene process. Since copper has a better heat conduction capability than tungsten, the semiconductor device has a better heat radiating capability than if the vias in all the layers were formed of tungsten.
The vias formed of copper beneath the power and ground lines have inside diameters greater than the inside diameters of the vias formed of tungsten beneath the signal lines by a predetermined proportion. The proportion is such that the mechanical strength of the vias formed beneath the power and ground lines is equal to or greater than the mechanical strength of the vias formed beneath the signal lines (specifically, greater by 12.9 times). Therefore, a reduction in the mechanical strength due to the vias being formed of copper is suppressed.
According to the present invention, furthermore, a semiconductor device having a plurality of at least six interconnection layers formed on a semiconductor substrate includes vias formed of tungsten in the first through third interconnection layers according to a single damascene process, interconnections formed of copper in the first through third interconnection layers according to a single damascene process, and vias and interconnections formed of copper in the interconnection layers higher than the third interconnection layer according to a dual damascene process. Since copper has a better heat conduction capability than tungsten, the semiconductor device has a better heat radiating capability than if the vias in all the layers were formed of tungsten.
The vias formed of copper in the interconnection layers higher than the third interconnection layer have inside diameters greater than the inside diameters of the vias formed of tungsten in the first through third interconnection layers by a predetermined proportion. The proportion is such that the mechanical strength of the vias in the interconnection layers higher than the third interconnection layer is equal to or greater than the mechanical strength of the vias in the first through third interconnection layers (specifically, greater by 12.9 times). Therefore, a reduction in the mechanical strength due to the vias being formed of copper is suppressed.
The above proportion determines not only the inside diameters of the vias formed of copper, but the number of vias in a location for interconnecting interconnection layers if the inside diameters of all the vias are equal to each other.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.